Hi,
We are working on Renesas RZ/N1D for product development. I wanted to transfer the data between two core (CM3 to CA7 and vicevarsa) between the cores and need to use the share memory to read/write the data. I have checked some documents related to MCTC data read/write and tested with example code (rzn1d_MCTC_osless_sample - CM3) provided by renesas, but it didn't work. I am getting below message after running the MCTC test.
Please help me to rectify the issue.