Hi,
I have the RZA1 RSK V2 board with the 800x480 LCD attached. I can run Qt5 apps in fb0 and everything is working great.
Now I want to decrease the amount of RAM used for fb0 - I do not need 800x480 resolution. I tried to modify the code beginning at line 338 in board-rskrza1.c that deals with the framebuffer to draw to the screen in a smaller resolution. I tried multiple different times to change the resolution to smaller values like 400x240 and 320x240. The screen changes, but displays garbage.
How can I achieve using a smaller FB0 on the RSK? Thanks.
Code I modified:
/* BOARD: Define your [LCD0] frame buffer location and size. */
#if XIP_KERNEL_WITHOUT_EXTERNAL_RAM
#define VDC5_0_BPP 16 /* 16bpp or 32bpp */
#define VDC5_0_FBSIZE (800*480*VDC5_0_BPP/8)
#define VDC5_0_FB_ADDR 0 /* allcoate at probe */
#else
#define VDC5_0_BPP 16 /* 16bpp or 32bpp */
#define VDC5_0_FBSIZE (800*480*VDC5_0_BPP/8)
/* Assume we are using external SDRAM for system memory so we have all
the internal memory just for our LCD frame buffer */
/* Place at end of internal RAM, but on a PAGE boundry */
//#define VDC5_0_FB_ADDR ((0x20A00000 - VDC5_0_FBSIZE) & PAGE_MASK)
/* Fixed allocation */
#define VDC5_0_FB_ADDR (0x60000000) /* PAGE 0 (2MB) */
#endif
static const struct resource vdc5fb0_resources[VDC5FB_NUM_RES] __initconst = {
[0] = DEFINE_RES_MEM_NAMED(0xfcff6000, 0x00002000, "vdc5fb.0: reg"),
[1] = DEFINE_RES_MEM_NAMED(VDC5_0_FB_ADDR, VDC5_0_FBSIZE, "vdc5fb.0: fb"),
[2] = DEFINE_RES_NAMED(75, 23, "vdc5fb.0: irq", IORESOURCE_IRQ),
};
static int vdc5fb_0_pinmux(struct platform_device *pdev)
{
size_t n, total;
struct pfc_pinmux_assign *pf;
struct vdc5fb_pdata *pdata
= (struct vdc5fb_pdata *)pdev->dev.platform_data;
/* Assign the LCD_0 pins */
pf = lcd0_common;
total = ARRAY_SIZE(lcd0_common);
for (n = 0; n < total; pf++, n++)
r7s72100_pfc_pin_assign(pf->port, pf->mode, DIIO_PBDC_DIS);
/* Assing only the TCON_0 pins that will be used */
pf = lcd0_tcon;
total = ARRAY_SIZE(lcd0_tcon);
for (n = 0; n < total; pf++, n++)
if (pdata->tcon_sel[n] != TCON_SEL_UNUSED)
r7s72100_pfc_pin_assign(pf->port, pf->mode, DIIO_PBDC_DIS);
return 0;
}
/* This structure defines the panel timings */
/* BOARD: You should rename this strucutre to match your LCD panel */
static struct fb_videomode videomode_gwp0700cnwv04 = {
.name = "gwp0700cnwv04",
.refresh = 60,
.xres = 800,
.yres = 480,
.pixclock = PIXCLOCK(P1CLK, 2),
.left_margin = 210, /* horizontal front porch */
.right_margin = 46, /* horizontal back porch */
.upper_margin = 23, /* vertical back porch */
.lower_margin = 22, /* vertical front porch */
.hsync_len = 40, /* max */
.vsync_len = 20, /* max */
.sync = 0,
.vmode = 0,
.flag = 0,
};
#if 0 /* FLOATING LAYER SAMPLE */
/* Graphics 3 - Image Synthesizer */
/* Creates a 200x200 32-bit ARGB floating layer */
#if XIP_KERNEL_WITHOUT_EXTERNAL_RAM
uint8_t gr3_fb[ 200*200*4 ] __attribute__ ((aligned (PAGE_SIZE)));
#else
#define gr3_fb 0x60600000 /* hard coded */
#endif
#endif
/* BOARD: You should rename this strucutre to match your LCD panel */
/* This structure passing info to the VDC5 driver */
static const struct vdc5fb_pdata vdc5fb_gwp0700cnwv04_pdata = {
.name = "gwp0700cnwv04",
.videomode = &videomode_gwp0700cnwv04,
.panel_icksel = ICKSEL_P1CLK, /* see include/video/vdc5fb.h */
.bpp = VDC5_0_BPP,
.panel_width = 154, /* mm, unused */
.panel_height = 86, /* mm, unused */
.flm_max = 1,
.out_format = OUT_FORMAT_RGB888,
.use_lvds = 0,
.tcon_sel = {
[LCD_TCON0] = TCON_SEL_UNUSED, /* MODE */
[LCD_TCON1] = TCON_SEL_UNUSED, /* DITH */
[LCD_TCON2] = TCON_SEL_DE, /* RGB_EN */
[LCD_TCON3] = TCON_SEL_STH, /* RGB_HSYNC */
[LCD_TCON4] = TCON_SEL_STVA, /* RGB_VSYNC */
[LCD_TCON5] = TCON_SEL_UNUSED, /* LR_INV */
[LCD_TCON6] = TCON_SEL_UNUSED, /* UD_INV */
},
.pinmux = vdc5fb_0_pinmux,
.layers = {
/* Graphics 2 - Image Synthesizer */
/* Full LCD Panel - will be /dev/fb0 */
[2].xres = 800,
[2].yres = 480,
[2].x_offset = 0,
[2].y_offset = 0,
#if VDC5_0_BPP == 16
[2].format = GR_FORMAT(GR_FORMAT_RGB565) | GR_RDSWA(6),
#else
[2].format = GR_FORMAT(GR_FORMAT_ARGB8888) | GR_RDSWA(4),
#endif
[2].bpp = VDC5_0_BPP,
[2].base = VDC5_0_FB_ADDR,
[2].blend = 0,
#if 0 /* FLOATING LAYER SAMPLE */
/* Graphics 3 - Image Synthesizer */
/* Creates a 200x200 32-bit ARGB floating layer */
[3].xres = 200,
[3].yres = 200,
[3].x_offset = 100,
[3].y_offset = 50,
[3].format = GR_FORMAT(GR_FORMAT_ARGB8888) | GR_RDSWA(4),
[3].bpp = 32,
[3].base = (u32)gr3_fb,
[3].blend = 1,
#endif
},
};
static const struct platform_device_info vdc5fb0_info __initconst = {
.name = "vdc5fb",
.id = 0, /* ch 0 */
.res = vdc5fb0_resources,
.num_res = ARRAY_SIZE(vdc5fb0_resources),
.data = &vdc5fb_gwp0700cnwv04_pdata,
.size_data = sizeof(vdc5fb_gwp0700cnwv04_pdata),
.dma_mask = DMA_BIT_MASK(32), /* only needed if not hardcoding fb */
};