RCAR H3 BOOTING ISSUE

Hi,


I am using RCAR H3 SIP module in my design.

For initial boot up of the processor I am using an external SPI flash as boot loader.

All the processor supply has been sequenced & the Processor input reset (PRESET) has been released.

Processor released the output reset (PRESETOUT) to peripherals.

But the clock(QSPI0_SPCLK) & chip select(QSPI0_SSL) of the QSPI  has not been asserted by processor.


By debugging it has been found that the delay between Processor reset in (PRESET) & processor reset out (PRESETOUT) is 8ms.


Can anyone let me know the probable cause of this issue ?

Regards,

Soumya