Hi nils,
I have following doubts regarding your setup,
1. Have you checked whether the SCL/SDA line of channel 1 is pulled down to low by the device connected (The SCL/SDA line should be high after the reset, if the bus is free).
2. Which clock rate are you trying to set, also what is the value of P0 Clock used (I couldn't find the values you mentioned for cks, brl and brh in the datasheet).
Also could you do the initialization cycle as shown below,
// Initial settings
RIIC1.RIICnCR1.UINT8[0] &= ~RIICn_RIICnCR1_ICE; // Clear ICE: output pins not driven (ICE = 0)
RIIC1.RIICnCR1.UINT8[0] |= RIICn_RIICnCR1_IICRST; // Set IICRST: RIIC reset (IICRST = 1)
RIIC1.RIICnCR1.UINT8[0] |= RIICn_RIICnCR1_ICE; // Set ICE: Internal reset (ICE = 1)
RIIC1.RIICnCR1.UINT8[0] &= ~RIICn_RIICnCR1_IICRST;// Release reset (IICRST = 0)
// Bit rate
RIIC1.RIICnMR1.UINT8[0] |= 0x10; // P0/2
RIIC1.RIICnBRL.UINT8[0] = 18; // TODO
RIIC1.RIICnBRH.UINT8[0] = 19; // TODO
RIIC1.RIICnFER.UINT8[0] |= RIICn_RIICnFER_NACKE; // Everything else default
// Set interrupts
RIIC1.RIICnIER.UINT32 = 0; // TODO