Hi Nils,
BRL and BRH are for setting duty cycle of SCL (width of low level and high level respectively), this value along with the cks value will determine your IIC data transfer rate, you can find the equation for transfer-rate in the data sheet. For e.g. For my board (RZ/A1H), the equation is:
Transfer rate = 1 / {[(RIICnBRH + 1) + (RIICnBRL + 1)] / IICφ + SCL line rising time [tr] + SCL
line falling time [tf]}
Duty cycle = {SCL line rising time [tr] + (RIICnICBRH + 1) / IICφ} / {SCL line falling time [tf]+
(RIICnBRL + 1) / IICφ}
where:
IICφ = P0φ × Division ratio
The SCL line rising time [tr] and SCL line falling time [tf] depend on the total bus line capacitance [Cb] and
the pull-up resistor [Rp]. For details, see the I2C bus standard from NXP Semiconductors.
And for 33Mhz, P0 clock,I'll use the following values for getting 100khz
cks, P0/8 -> 0x3
BRL, 19 -> 0xF3 //The write value to the bits 5 to 7 of BRL should be 1
BRH, 16 -> 0xF0 //The write value to the bits 5 to 7 of BRH should be 1
Also, regarding the initialization cycle, I assume you are doing this initialization sequence every time for each Start condition issuance,
i.e. init->BBSY check -> Start condition -> <data transfer> ->Stop condition(finish), init->BBSY check -> Start condition -> <data transfer> -> Stop condition(finish)...
because I'd trouble in getting BBSY 0 sigal when I did this initialization only once.