Hello,
On RZ/T1 how do I activate the instruction cache for the Instruction RAM? The bits SCTLR.I and SCTLR.C are set to 1. If I then activate the cache in the MPU (DRACR) for that region, I get prefetch exception. If I step the code with the debugger, the functions in this memory range are executed normally.
I used the same MPU cache settings for the SDRAM (CS3) region and it worked fine, no prefetch exception occurred.