Can someone point me to docs explaining the format of the TLB entries?

I'm trying to understand the format of the TLB entries (at least as used in the RZ/A1 Framework, app note R01AN3638EJ0103).

I've tried reading the Cortex A-9 Technical Reference Manual - but that isn't doing the trick for me.

All I need is an explanation of which bits control which features (caching, R/W, Execute, etc.)

Thanks.