RZ/A1H , LVDS interface to DVI

The processor has a module for providing a low voltage differential signaling (LVDS) output interface. This module converts the RGB signals output from video display controller 5 to the LVDS format that has six bits each for R, G, and B signals,
and outputs the converted signals. It has a dedicated phase-locked loop (PLL) circuit, which can generate a clock with a desired frequency by dividing or multiplying the input clock frequency.
The clock output from this PLL can be used as the panel clock for video display controller 5 even when LVDS output is not used. This PLL is called LVDS PLL in this section.
• Four pairs of differential output conforming to the TIA/EIA-644 standard (three pairs for data and one pair for the
clock) 
TXOUT0P
TXOUT0M
TXOUT1P
TXOUT1M
TXCLKOUTP
TXCLKOUTM
TXOUT2P
TXOUT2M

how can i use these signals to output to DVI