Hi,
Im working on a display connected with LVDS to an RZ/A1H. As the title says, i'm not having any luck ;).
The display is the sharp 'lq070y3lg4a', and I have added a new board that i've configured to make use of ch0-LVDS.
Since this is the first time i'm working on a custom linux distro with LCD, im not sure what I am doing wrong here..
The configurations i have made in my DTS are given below, does anybody know what steps I should take to get the display working?
#define VDC5_0_BPP 32 /* 16bpp or 32bpp */
#define VDC5_0_FBSIZE (800*480*VDC5_0_BPP/8)
#define VDC5_0_FB_ADDR 0 /* allocate memory at probe */
&vdc50 {
pinctrl-names = "default";
pinctrl-0 = <&vdc50_pins>;
display = <&display0>;
status = "okay";
panel_name = "lq070y3lg4a";
/* Set the physical frame buffer address for internal RAM. */
fb_phys_addr = <VDC5_0_FB_ADDR>;
fb_phys_size = <VDC5_0_FBSIZE>;
panel_pixel_xres = <800>; /* panel native resolution */
panel_pixel_yres = <480>; /* panel native resolution */
/* Double Buffering. Reserves 2x memory space as frame buffer */
/* Use "ioctl(fb0_fd, FBIOPAN_DISPLAY, &var)" from application
* space to change "var.yoffset=Y" where 'Y' is from 0 to var.yres
*/
//double_buffer; /* Uncomment for double buffering */
/* See 'drivers/video/fbdev/renesas/vdc5fb.h' for valid choices
* for panel_icksel, panel_ocksel, and out_format */
panel_icksel = <3>; /* 3=ICKSEL_P1CLK (Peripheral clock 1) */
panel_ocksel = <0>; /* (don't care when lvds=0 ) */
out_format = <0>; /* 0=OUT_FORMAT_RGB888 */
use_lvds = <1>; /* Set to 0 or 1 */
display0: display0 {
compatible = "lvds-panel";
source = "lvds.0";
bits-per-pixel = <VDC5_0_BPP>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33325000>;
hactive = <800>;
vactive = <480>;
hback-porch = <35>; /* back porch = 'HS Blanking'(46) - hsync-len(20) */
hfront-porch = <5>; /* 'HS Front Porch (210)' */
vback-porch = <35>; /* back porch = 'VS Blanking'(23) - vsync-len(10) */
vfront-porch = <3>; /* 'VS Front Porch(22)' */
hsync-len = <1056>; /* pulse width of HSYNC (min=1, max=40) */
vsync-len = <525>; /* pulse width of VSYNC (min=1, max=20) */
hsync-active = <127>; /* HSYNC pulse is: 0=Active LOW, 1=Active HIGH */
vsync-active = <2>; /* VSYNC pulse is: 0=Active LOW, 1=Active HIGH */
de-active = <1>; /* Data Enable signal is: 0=Active LOW , 1= Active HIGH */
pixelclk-active = <1>; /* Pixel Data clock polarity: 0=drive pixel data on falling edge and sample data on rising edge */
};
};
};
};
