Hello,
I try to add dynamic calculation for LVDS PLL settings by given input frequency (FIN) and output frequency (FOUT). But if I use equations from manual (section 21.3) and set LPLLSETR register to calculated values I messure wrong FOUT.
Do anyone used LVDS register settings on G1C? Maybe I did a mistake in my calculation. Thank you.
In my case I use:
IN clock -> Pphi - Peripheral Clock (65MHz); so FIN=65MHz/4 = 16,25 MHz is in the range [9..30]MHz
FOUT = 30MHz * (Frequency divider 2) = 30MHz*7 = 210MHz
LVDSPLL_OD = 2 means NOD = 4 because NOD=2^LVDSPLL_OD
FVCO = 30MZh*7 * 4 = 840 MHz is in the give range [750..1630]MHz
Becaue FOUT should be (FIN*NFD)/(NRD*NOD). NFD/NRD = FOUT * NOD /FIN so NFD/NRD = 210MHz*4/16,25MHz it is about 52
NRD have to be 1 because freq. range is [2.5..30]MHz; so NFD have to be 52.
840MHz/52 = 16,15Mhz... It is in the range [9..30]MHz too.
All of this register values are allowed as per manual. But I messure about 120Mhz what is wrong...