Hello,
I have a question about de RZ-A1H, with the case VDC5 and frame buffer underflow.
For the LCD attached to the VDC5 module there will be data read continuly from internal RAM (I have set it to adres 0x60100000, no cache and orther *** in MMU)
Frame buffer transfer mode is 32 byte, and format is RGB888 (so 4 bytes per pixel). just 1 frame buffer. (plane 2)
ClockSpeed (panel clock) for the VDC5 module (via LVDS PLL and div by 7) is about 81 Mhz, clockspeed processor is 360 Mhz (12 Mhz input freq multiply by 30)
What I see, is that de frame buffer in the VDC5 module not get enough time to get his data from RAM, while the main loop in de software nothing has to do (just while(1) in memory 0x20003Fxx, cache enabled and so on.
When I set the format to RGB 565 (so 2 bytes per pixel) there is no problem. Also lower the LVDS clock (62 Mhz and lower) and the problem is gone.
For the internal ram, the databus is 32 bits, and clocked at 120 Mhz (B0), is that correct?
Any idea? Is it possible that because 2 diferent not coherent clocks (LVDS 81 Mhz and ram B0 120 Mhz) something is delayed?
Thank's for help!