interrupt priorities - RZ/A1 Serial communication interface with FIFO

Hi 

We are using RZ/A1 processor based custom target board . linux kernel version is 4.9.123 ( downloaded from renesas site).

user manual r01uh0403ej0200_rz_a1h pdf is referred .

i am using serial communiction interface with FIFO . i observed it has 8 channels .

each channel has its own interrupt id ( table 7.3 , page 240 ) for each of its interrupt event .

i have a question about interrupt priority . 

if channel 0 and channel 1 TXI or RXI interrupt comes at the same time , which interrupt will be serviced first by the gic ?

does any channel  has higher priority for its interrupt to be serviced  with respect to other channel ?