Hi,
Thank you for the previous help
With Linux 4.9, a tfp410 dvi output transmitter attached to the LCD_0 output of the RZ/A1, and a computer monitor attached over hdmi, I am trying to set the output resolution to 800x600 at 60 hz
When using settings in the device tree dts file from an RSK evaluation board for 800x480, the monitor says that the resolution is 640x480@53 hz.
Decreasing the resolution to 640x480, causes the attached monitor to show that the resolution is 640x480@63hz.
When trying to increase the resolution to 800x600, the monitor gives a signal out of range error.
" //this mode works but causes the monitor to show 63 hz
timing1: timing1{
//640x480 @ 63 hz
clock-frequency = <33325000>; /* P1 clk / 2 */
hactive = <640>;
vactive = <480>;
hback-porch = <26>; /* back porch = 'HS Blanking'(46) - hsync-len(20) */
hfront-porch = <210>; /* 'HS Front Porch (210)' */
vback-porch = <13>; /* back porch = 'VS Blanking'(23) - vsync-len(10) */
vfront-porch = <22>; /* 'VS Front Porch(22)' */
hsync-len = <20>; /* pulse width of HSYNC (min=1, max=40) */
vsync-len = <10>; /* pulse width of VSYNC (min=1, max=20) */
hsync-active = <1>; /* HSYNC pulse is: 0=Active LOW, 1=Active HIGH */
vsync-active = <1>; /* VSYNC pulse is: 0=Active LOW, 1=Active HIGH */
de-active = <0>; /* Data Enable signal is: 0=Active LOW , 1= Active HIGH */
pixelclk-active = <0>; /* Pixel Data clock polarity: 0=drive pixel data on falling edge and sample data on rising edge */
};
"
"//this mode causes the monitor to show unsupported resolution
timing0: timing0 {
clock-frequency = <40000000>;
hactive = <800>;
hfront-porch = <40>; /* 'HS Front Porch (210)' */
hsync-len = <128>; /* pulse width of HSYNC (min=1, max=40) */
hback-porch = <88>; /* back porch = 'HS Blanking'(46) - hsync-len(20) */
hsync-active = <1>; /* HSYNC pulse is: 0=Active LOW, 1=Active HIGH */
vactive = <600>;
vfront-porch = <1>; /* 'VS Front Porch(22)' */
vsync-len = <4>; /* pulse width of VSYNC (min=1, max=20) */
vback-porch = <23>; /* back porch = 'VS Blanking'(23) - vsync-len(10) */
vsync-active = <1>; /* VSYNC pulse is: 0=Active LOW, 1=Active HIGH */
de-active = <0>; /* Data Enable signal is: 0=Active LOW , 1= Active HIGH */
pixelclk-active = <0>; /* Pixel Data clock polarity: 0=drive pixel data on falling edge and sample data on rising edge */
};
"
I have tried different settings for clock-frequency but it seems that the pixel clock is staying the same because higher resolutions
cause the refresh rate to decrease.
Are there settings that have been tested for different output resolutions available?
Many Thanks