Hi all,
I am using RZ/A2M custom board, i have enabled 64MB SDRAM successfully, now i am trying to enable 128MB SDRAM and the configuration is 16-bit of 2 chips(SDRAMs) sharing same address pins (A1-A15) and data pins(D0-D15) but different CS pins, i am using CS2 and CS3, i have taken genmai board reference u-boot and dts files but the board is not booting plz help me to resolve this issue.
this is what i have changed in u-boot file SDRAM section
/* SDRAM */
#ifdef RZA2M_ENABLE_SDRAM
/* D0 - D15 */
for(i = 0; i <= 6; i++)
pfc_set_pin_function(P0, i, 1); /* P0_0~6 = D0-D6 */
for(i = 0; i <= 4; i++)
pfc_set_pin_function(P1, i, 1); /* P1_0~4 = D7-D11 */
for(i = 0; i <= 3; i++)
pfc_set_pin_function(P2, i, 1); /* P1_0~3 = D12-D15 */
/* A1 - A15 */
for(i=1;i<=7;i++)
pfc_set_pin_function(P8, i, 1); /* P8_1~7: A1-A7 */
for(i=0;i<=7;i++)
pfc_set_pin_function(P9, i, 1); /* P9_0~7 = A8-A15 */
pfc_set_pin_function(P6, 5, 1); /* P6_5 = CS3 */
pfc_set_pin_function(P6, 6, 1); /* P6_6 = CS2 */
pfc_set_pin_function(P7, 3, 1); /* P7_3 = RAS */
pfc_set_pin_function(P7, 4, 1); /* P7_4 = CAS */
pfc_set_pin_function(P7, 5, 1); /* P7_5 = CKE */
pfc_set_pin_function(P7, 1, 1); /* P7_1 = RD/WR */
pfc_set_pin_function(P6, 7, 1); /* P6_7 = WE0/DQMLL */
pfc_set_pin_function(P7, 0, 1); /* P7_0 = WE1/DQMLU */
#endif
/* LED */
pfc_set_gpio(P6, 0, GPIO_OUT); /* P6_0 = GPIO_OUT */
pfc_set_gpio(PC, 1, GPIO_OUT); /* PC_1 = GPIO_OUT */
//led_red_set_state(1);
//led_green_set_state(1);
#ifdef RZA2M_ENABLE_HYPERRAM
/* Hyper RAM */
HyperRAM_Init();
#endif
/* NOTE: You can't use SDRAM and SCIF4 (serial console) at the same time because
they share the same pins. */
#if (SW6_1 == SW_ON)
/**********************************************/
/* Configure SDRAM (CS3) */
/**********************************************/
#define CS2BCR_D 0x00004C00 /* (CS2) Type=SDRAM, 16-bit memory */
#define CS2WCR_D 0x00000500 /* (CS2) CAS Latency = 2 */
#define CS3BCR_D 0x00004C00 /* (CS3) Type=SDRAM, 16-bit memory */
//#define CS3WCR_D 0x00002D13 /* */
#define CS3WCR_D 1 << 13 | /* (CS2,CS3) WTRP (1 cycles) */\
3 << 10 | /* (CS2,CS3) WTRCD (3 cycles) */\
2 << 7 | /* (CS3) A3CL (CAS Latency = 3) */\
2 << 3 | /* (CS2,CS3) TRWL (2 cycles) */\
3 << 0 /* (CS2,CS3) WTRC (5 cycles) */
#define SDCR_D 0x00120812 /* 13-bit row, 10-bit col, auto-refresh */
/*
* You must refresh all rows within the amount of time specified in the memory spec.
* Total Refresh time = [Number_of_rows] / [Clock_Source / Refresh Counter]
* 63.55ms = [2^13] / [(132MHz / 16) / 64]
*/
/* SDRAM : 8K refresh cycles every 64ms */
#define RTCOR_D 0xA55A0040 /* Refresh Counter = 64 */
#define RTCSR_D 0xA55A0010 /* Clock Source=CKIO/16 (CKIO=132MHz) */
*(u32 *)CS2BCR = CS2BCR_D;
*(u32 *)CS2WCR = CS2WCR_D;
*(u32 *)CS3BCR = CS3BCR_D;
*(u32 *)CS3WCR = CS3WCR_D;
*(u32 *)SDCR = SDCR_D;
*(u32 *)RTCOR = RTCOR_D;
*(u32 *)RTCSR = RTCSR_D;
/* wait */
#define REPEAT_D 0x000033F1
for (i=0;i<REPEAT_D;i++) {
asm("nop");
}
/* AC Characteristics Adjustment Register (ACADJ) */
#define ACADJ 0x1F000090
*(u32 *)ACADJ = 0x0002000F; /* fixed value */
/* The final step is to set the SDRAM Mode Register by written to a
specific address (the data value is ignored) */
/* Check the hardware manual (table 8.11) if your settings differ */
/* Burst Length = 1 (fixed)
* Burst Type = Sequential (fixed)
* CAS Latency = 2 or 3 (see table 8.11)
* Write Burst Mode = [burst read/single write] or [burst read/burst write] (see table 8.15)
*/
//#define SDRAM_MODE_CS2 0x1F001440 /* CS2: CAS=2, single write, 16bit bus */
//#define SDRAM_MODE_CS3 0x1F002440 /* CS3: CAS=2, single write, 16bit bus */
//#define SDRAM_MODE_CS2 0x1F001460 /* CS2: CAS=3, single write, 16bit bus */
//#define SDRAM_MODE_CS3 0x1F002460 /* CS3: CAS=3, single write, 16bit bus */
//#define SDRAM_MODE_CS2 0x1F002040 /* CS2: CAS=2, burst write, 16bit bus */
//#define SDRAM_MODE_CS3 0x1F002040 /* CS3: CAS=2, burst write, 16bit bus */
//#define SDRAM_MODE_CS2 0x1F002060 /* CS2: CAS=3, burst write, 16bit bus */
#define SDRAM_MODE_CS2 0x1F002040 /* CS2: CAS=3, burst write, 16bit bus */
//#define SDRAM_MODE_CS3 0x1F002060 /* CS3: CAS=3, burst write, 16bit bus */
#define SDRAM_MODE_CS3 0x1F002040 /* CS3: CAS=3, burst write, 16bit bus */
*(u16 *)SDRAM_MODE_CS2 = 0;
*(u16 *)SDRAM_MODE_CS3 = 0;
#endif
int board_init(void)
{
gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
return 0;
}
#ifdef CONFIG_SH_ETHER
int board_eth_init(bd_t *bis)
{
int ret = -ENODEV;
ret = sh_eth_initialize(bis);
return ret;
}
#endif
int board_mmc_init(bd_t *bis)
{
int ret = 0;
ret |= sh_sdhi_init(CONFIG_SYS_SH_SDHI0_BASE,
0,
SH_SDHI_QUIRK_64BIT_BUF);
ret |= sh_sdhi_init(CONFIG_SYS_SH_SDHI1_BASE,
1,
SH_SDHI_QUIRK_64BIT_BUF);
return ret;
}
int board_late_init(void)
{
u8 mac[6]={0x74, 0x90, 0x50, 0xC0, 0xFE, 0x06};
u8 senddata[2];
char line1[] = "\t\t | |\n";
char line2[] = "\t\t | |\n";
char on_off[] = "= ";
char off_on[] = " =";
char SW6_1_str[2][10] = {"SDRAM","Other"};
char SW6_2_str[2][10] = {"DRP","Audio"};
char SW6_3_str[2][30] = {"DRP","USB, CAN, UART(console)"};
char SW6_4_str[2][10] = {"Ether1","CEU"};
char SW6_5_str[2][10] = {"Ether2","NAND"};
char SW6_6_str[2][10] = {"VDC6","NAND"};
char SW6_7_str[2][10] = {"VDC6","SIM"};
/* Increase the clock speed of the QSPI
* P0(33MHz) -> B(132MHz)
* SPI clock pin will be 1/2 the IP peripheral speed (66MHz) */
*(volatile u16 *)SCLKSEL |= 2; /* QSPI Clock = B */
if (is_valid_ethaddr(mac))
eth_setenv_enetaddr("ethaddr", mac);
#if 1 /* Enable the TFP410 Digital Transmitter */
/* (some kits do not come with LCD displays) */
senddata[0] = (uint8_t)(0x08u); // reg address
senddata[1] = (uint8_t)(0xbdu);
/* Init I2C-3 bus for TFP410 */
i2c_init(100000, 0); /* speed = 100kHz */
i2c_set_bus_num(3); /* I2C ch-3 */
/* Slave = 0x78 (HW manual says 0x78, but really it's 7-bit address is 0x3C)*/
i2c_write((0x78 >> 1), senddata[0], 1, senddata+1, 1);
#endif
#if 1 /* Single QSPI flash */
printf( "\t\t SPI Flash Memory Map\n"
"\t\t------------------------------------\n"
"\t\t Start Size\n");
printf( "\t\tu-boot: 0x%08X 0x%06X\n", 0,CONFIG_ENV_OFFSET);
printf( "\t\t env: 0x%08X 0x%06X\n", CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE);
printf( "\t\t DT: 0x%08X 0x%06X\n", 0xC0000,CONFIG_ENV_SECT_SIZE);
printf( "\t\tKernel: 0x%08X 0x%06X\n",0x200000, 0x50000);
printf( "\t\trootfs: 0x%08X 0x%06X\n",0x800000, 0x400000 - 0x800000);
#else /* Dual QSPI flash */
printf( "\t\t SPI Flash Memory Map\n"
"\t\t------------------------------------\n"
"\t\t Start Size SPI\n");
printf( "\t\tu-boot: 0x%08X 0x%06X 0\n", 0,CONFIG_ENV_OFFSET);
printf( "\t\t env: 0x%08X 0x%06X 0\n", CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE);
printf( "\t\t DT: 0x%08X 0x%06X 0\n", 0xC0000,CONFIG_ENV_SECT_SIZE);
printf( "\t\tKernel: 0x%08X 0x%06X 0+1 (size*=2)\n",0x100000, 0x280000);
printf( "\t\trootfs: 0x%08X 0x%06X 0+1 (size*=2)\n",0x400000, 0x2000000-0x400000);
#endif
/* SW6 Settings */
line1[5] = on_off[SW6_1];
line1[7] = on_off[SW6_2];
line1[9] = on_off[SW6_3];
line1[11] = on_off[SW6_4];
line1[13] = on_off[SW6_5];
line1[15] = on_off[SW6_6];
line1[17] = on_off[SW6_7];
line2[5] = off_on[SW6_1];
line2[7] = off_on[SW6_2];
line2[9] = off_on[SW6_3];
line2[11] = off_on[SW6_4];
line2[13] = off_on[SW6_5];
line2[15] = off_on[SW6_6];
line2[17] = off_on[SW6_7];
printf( "\n");
printf( "\t\t ON SW6\n");
printf( "\t\t +---------------------+\n");
printf(line1);
printf(line2);
printf( "\t\t | 1 2 3 4 5 6 7 8 9 0 | Please make sure your sub-board matches\n");
printf( "\t\t +---------------------+ these switch settings.\n");
printf( "\tSW6-1 set to %s\n",SW6_1_str[SW6_1]);
printf( "\tSW6-2 set to %s\n",SW6_2_str[SW6_2]);
printf( "\tSW6-3 set to %s\n",SW6_3_str[SW6_3]);
printf( "\tSW6-4 set to %s\n",SW6_4_str[SW6_4]);
printf( "\tSW6-5 set to %s\n",SW6_5_str[SW6_5]);
printf( "\tSW6-6 set to %s\n",SW6_6_str[SW6_6]);
printf( "\tSW6-7 set to %s\n",SW6_7_str[SW6_7]);
printf( "\n");
/* Default addresses */
#define DTB_ADDR_FLASH "C0000" /* Location of Device Tree in QSPI Flash (SPI flash offset) */
#define DTB_ADDR_RAM "20500000" /* Internal RAM location to copy Device Tree */
#define DTB_ADDR_SDRAM "09800000" /* External SDRAM location to copy Device Tree */
#define MEM_ADDR_RAM "0x20000000 0x00A00000" /* System Memory for when using on-chip RAM (10MB) */
#define MEM_ADDR_SDRAM "0x08000000 0x08000000" /* System Memory for when using external SDRAM RAM (64MB) */
#define KERNEL_ADDR_FLASH "0x20200000" /* Flash location of xipImage or uImage binary */
#define UIMAGE_ADDR_SDRAM "09000000" /* Address to copy uImage to in external SDRAM */
#define UIMAGE_ADDR_SIZE "0x400000" /* Size of the uImage binary in Flash (4MB) */
/* Default kernel command line options */
setenv("cmdline_common", "ignore_loglevel earlycon");
/* Root file system choices */
setenv("fs_axfs", "rootfstype=axfs rootflags=physaddr=0x18800000");
setenv("fs_mtd", "root=/dev/mtdblock0");
/* LCD Frame buffer location */
setenv("dtb_lcdfb_fixed", "fdt set /display@fcff7400 fb_phys_addr <0x60000000>"); /* Fixed address */
setenv("dtb_lcdfb_dyn", "fdt set /display@fcff7400 fb_phys_addr <0x00000000>"); /* Dynamically allocate during boot */
/* Read DTB from Flash into either internal on-chip RAM or external SDRAM */
setenv("dtb_read_ram", "sf probe 0; sf read "DTB_ADDR_RAM" "DTB_ADDR_FLASH" 8000; fdt addr "DTB_ADDR_RAM" ; setenv addr_dtb "DTB_ADDR_RAM"");
setenv("dtb_read_sdram", "sf probe 0; sf read "DTB_ADDR_SDRAM" "DTB_ADDR_FLASH" 8000; fdt addr "DTB_ADDR_SDRAM" ; setenv addr_dtb "DTB_ADDR_SDRAM"");
/* Set the system memory address and size. This overrides the setting in Device Tree */
setenv("dtb_mem_ram", "fdt memory "MEM_ADDR_RAM""); /* Use internal RAM for system memory */
setenv("dtb_mem_sdram", "fdt memory "MEM_ADDR_SDRAM""); /* Use external SDRAM for system memory */
/* You have comment out the above line to get two sdram working nags*/
/* renesasrulz.com/.../external-memory-stream-it */
/* Kernel booting operations */
setenv("xImg", "qspi dual; setenv cmd bootx "KERNEL_ADDR_FLASH" ${addr_dtb}; run cmd"); /* Boot a XIP Kernel */
setenv("uImg", "qspi dual; cp.b "KERNEL_ADDR_FLASH" "UIMAGE_ADDR_SDRAM" "UIMAGE_ADDR_SIZE"; bootm start "UIMAGE_ADDR_SDRAM" - "DTB_ADDR_SDRAM"; bootm loados ; bootm go"); /* Boot a uImage kernel */
/* => run xa_boot */
/* Boot XIP using internal RAM only, file system is AXFS, LCD dynamically allocated */
//setenv("xa_boot", "run dtb_read_ram dtb_mem_ram dtb_lcdfb_dyn; setenv bootargs ${cmdline_common} ${fs_axfs}; fdt chosen; run xImg");
setenv("xa_boot", "cp.b 200c0000 80300000 10000 ; qspi single ; bootx 20200000 80300000");
/* => run xsa_boot */
/* Boot XIP using external 64MB SDRAM, file system is AXFS, LCD FB fixed to internal RAM */
//setenv("xsa_boot", "run dtb_read_sdram dtb_mem_sdram dtb_lcdfb_fixed; setenv bootargs ${cmdline_common} ${fs_axfs}; fdt chosen; run xImg");
setenv("xsa_boot", "cp.b 200c0000 0C300000 10000 ; qspi single ; bootx 20200000 0C300000");
/* => run xha_boot */
/* Boot XIP using external 8MB HyperRAM, file system is AXFS, LCD FB fixed to internal RAM */
setenv("xha_boot", "cp.b 200c0000 40300000 10000 ; qspi single ; bootx 20200000 40300000");
/* => run s_boot */
/* Boot SDRAM uImage using external 32MB SDRAM, file system is squashfs, LCD FB fixed to internal RAM */
setenv("s_boot", "run dtb_read_sdram dtb_mem_sdram dtb_lcdfb_fixed; setenv bootargs ${cmdline_common} ${fs_mtd}; fdt chosen; run uImg");
/* => run sa_boot */
/* Boot SDRAM uImage using external 32MB SDRAM, file system is AXFS, LCD FB fixed to internal RAM */
setenv("sa_boot", "run dtb_read_sdram dtb_mem_sdram dtb_lcdfb_fixed; setenv bootargs ${cmdline_common} ${fs_axfs}; fdt chosen; run uImg");
return 0;
this is what i have changed in dts file
memory@80000000 {
device_type = "memory";
#ifdef MEM_INTERNAL_RAM
reg = <0x80000000 0x00400000>; /* 4Mbyte of Internal RAM */
#endif
#ifdef MEM_HYPERRAM
reg = <0x40000000 0x00800000>; /* 8Mbyte of External HyperRAM */
#endif
#ifdef MEM_SDRAM
reg = <0x08000000 0x08000000 >; /* 64Mbyte * 2 of External SDRAM */
#endif
please respond
this is the configuration in u-boot RZ/A2M
Thanks and regards
Mahesh .R