JPEG Encoding Library for Gstreamer on RSK RZA1H
Hi,We are trying to bring up Gstreamer on RSK RZA1H. While functionally MJPEG is working, the frame rate is too low for even 640x480 resolution. It would help if internal JCU unit is used for encoding...
View ArticleRE: Program/Erase flash chip on RZ (CS0)
I believe I have solved my problem.For those who might care, I set up the TTB for the CS0 Mirror space (at address 0x40000000) to use a domain of 0xF (while the rest of the TTB entries use domain 0)....
View ArticleProgram/Erase flash chip on RZ (CS0)
My design executes code directly out of a flash chip on CS0. Now I need to be able to erase and program a portion of this chip for logging purposes.I wrote a simple routine to query the flash chip's...
View ArticleRE: RZ A1L Newby Pinout Question
SD does not use pin MMC_D4. That is only for eMMC (8-bit data).You only care about the pins that say SD_xxx38. SD Host Interface38.1.3 Input/Output PinsTable 38.1 Pin Configuration Pin Name Signal Name...
View ArticleRE: RZ A1L Newby Pinout Question
Thanks!! I should have gotten that on my own - Doh!!So how about something like the secondary QSPI flash - it seems to conflict with the A11, A12, A13, A14 pins. Are we limited to running a single...
View ArticleRE: RZ A1L Newby Pinout Question
From what I can remember, that one you might be stuck with.Your only other option is to buy a RZ/A1LU where they added DDR support to the QSPI. But, you just have to do the work of making sure the...
View ArticleRZ A1L Newby Pinout Question
I am working on a design using the RZ A1L part which is the 176 pin QFP. I am using the developer kit design as a starting point but am finding conflicts due to the limited number of pins on the QFP....
View ArticleRE: RZA1 RSK Adding Device Tree Node for MMC0
Hi Chris,Here are the steps required to get the Wilink 8 WiFi/Bluetooth/BLE radio to work with the Renesas RZA1 Dev Kit:Purchase the radio and the SD card adapter kit:...
View ArticleRE: RZ/A1 RSK Device Tree add WiFi/BT using SDIO interface with TI Wilink8
I added instructions on how to get the Wilink 8 to work here: renesasrulz.com/.../22503.aspx
View ArticleRE: RZA1 RSK Adding Device Tree Node for MMC0
Good instructions. Thank you for contributing!
View ArticleRE: XIP Kernel with Single Quad-SPI on RZ/A1 RSK
For the RSK the default was:u-boot = single SSPIdtbs = single QSPIkernel = dual QSPIrootfs = dual QSPIUsually the biggest confusion when moving between single and dual QSPI modes is the SPI addressing....
View ArticleRE: XIP Kernel with Single Quad-SPI on RZ/A1 RSK
I did flash the AXFS rootfs with the following CommanderScript as well but it did not seem to help:speed 100000device R7S721001rx 100exec SetCompareMode=0exec SetVerifyDownload=0exec...
View ArticleRE: XIP Kernel with Single Quad-SPI on RZ/A1 RSK
> I did flash the AXFS rootfs with the following CommanderScript as well but it did not seem to help:But, when you called the script, did you start JLinkExe with -device R7S721001or -device...
View ArticleRE: XIP Kernel with Single Quad-SPI on RZ/A1 RSK
I must have some kind of addressing issue. When I reflashed the Kernel, it booted fully. Whenever I seem to flash the rootfs, the subsequent kernel boot hangs. But if I then reflash the kernel, it...
View ArticleRE: RZ/A1L GPIO versus RZ/A1H GPIO
> The pin assignments differ on the RZ/A1L part. Is there a BSP for the RZ/A1L? How can I determine what the GPIO names are for the RZ/A1L? Thank you.For the most part, the pin assignments are the...
View ArticleRZ/A1L GPIO versus RZ/A1H GPIO
In the BSP for the RZA1H Dev Kit there is the following array of GPIO names:static const char * const gpio_names[] = {"P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5","P1_0", "P1_1", "P1_2", "P1_3",...
View ArticleRE: XIP Kernel with Single Quad-SPI on RZ/A1 RSK
> Whenever I seem to flash the rootfs, the subsequent kernel boot hangs.I think, it is because high byte of address is set up by "Bank Register Write" command, and after the system is reset and...
View ArticleXIP Kernel with Single Quad-SPI on RZ/A1 RSK
I need to boot the RZ/A1 RSK XIP Kernel out of a single Quad SPI instead of the dual Quad SPI default configuration of the dev kit. We removed the resistor R283 on the chip select line to I2C5 ( which...
View ArticleRE: What's the best way to do a software-controlled CPU reset?
You do a watchdog reset. That's what we do in the Linux BSP. It resets everything.
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