Hi,

We are trying to bring up Gstreamer on RSK RZA1H. While functionally MJPEG is working, the frame rate is too low for even 640x480 resolution. It would help if internal JCU unit is used for encoding the image. But we could not find the source/library for the same. Can you point us towards the same?

And any one has brought up MJPEG/H.264 on the RSK with decent rate?

Regards,

Raja.A.

I believe I have solved my problem.

For those who might care, I set up the TTB for the CS0 Mirror space (at address 0x40000000) to use a domain of 0xF (while the rest of the TTB entries use domain 0).  Then, I changed the DACR to give domain 15 (0xF) "Manager" access.  As I understand it, this bypasses the translation tables completely.

Whether this is a good fix or not, I can't say - but it seems to work, so I'm sticking with it...

My design executes code directly out of a flash chip on CS0.  Now I need to be able to erase and program a portion of this chip for logging purposes.

I wrote a simple routine to query the flash chip's device info, but everything I try just gets me the contents of flash (not the actual device info).

Is there a trick that I'm missing?  Our flash chip is a Spansion S29GL064S (8Mbyte, 16-bit).  Here's the code that I'm running:

void RAMFUNC ram_flash_status(uint32_t flashAddr) {
volatile uint16_t *flash555 = (uint16_t *)(0x555 * 2);
volatile uint16_t *flash2AA = (uint16_t *)(0x2AA * 2);
volatile uint16_t *flashPtr = (uint16_t *)flashAddr;
int idx;

// Read the device information
*flash555 = 0x00AA; // Cycle #1
*flash2AA = 0x0055; // Cycle #2
*flash555 = 0x0090; // Cycle #3

for (idx = 0; idx < DEVINFO_SIZE; idx++) {
flash_devinfo[idx] = flashPtr[idx];
}

// Issue Reset command
*flash555 = 0x00F0; // Cycle #1
}

SD does not use pin MMC_D4. That is only for eMMC (8-bit data).

You only care about the pins that say SD_xxx

38. SD Host Interface

38.1.3 Input/Output Pins

Table 38.1 Pin Configuration

Pin Name      Signal Name I/O    Function
SD_CLK[1:0]*1 SDCLK       Output SD clock
SD_CMD[1:0]*1 SDCMD       I/O    Command/response
SD_D0[1:0]*1  SDDAT0      I/O    Data[bit 0]
SD_D1[1:0]*1  SDDAT1      I/O    Data[bit 1]/SDIO interrupt
SD_D2[1:0]*1  SDDAT2      I/O    Data[bit 2]/Read wait
SD_D3[1:0]*1  SDDAT3      I/O    Data[bit 3]
SD_CD[1:0]*1  ISDCD       Input  Card detect*2
SD_WP[1:0]*1  ISDWP       Input  Write protect*2

Note 1. [1:0] indicates the SD Host Interface channel number.
Note 2. When a pin is not in use, fix the corresponding signal to 1.

Thanks!!  I should have gotten that on my own - Doh!!

So how about something like the secondary QSPI flash - it seems to conflict with the A11, A12, A13, A14 pins.  Are we limited to running a single QSPI chip instead of the dual configuration as in the developer kit?

From what I can remember, that one you might be stuck with.

Your only other option is to buy a RZ/A1LU where they added DDR support to the QSPI. But, you just have to do the work of making sure the timing of the DDR QSPI chip matches up with the RZ/A1LU. I was seeing an issue that I could not run the DDR QSPI part on the RSK at the full 66MHz clock because of the timing violations, and the next drop down was 33MHz (but then you are the same as the normal 66MHz SDR...so there was not point).

Thanks!!

I am working on a design using the RZ A1L part which is the 176 pin QFP.  I am using the developer kit design as a starting point but am finding conflicts due to the limited number of pins on the QFP. As an example, I am planning on using external SDRAM and an external SD Card slot.  In selecting the pins for this I see that pin 173 can be configured as D0 and as MMC_D4 but no other pins have either D0 or MMC_D4.  Is there a way around this which would be configured in software or is using SDRAM and an SD card mutually exclusive on this part?

Thanks

Nitro_GS_R

Hi Chris,

Here are the steps required to get the Wilink 8 WiFi/Bluetooth/BLE radio to work with the Renesas RZA1 Dev Kit:

• Purchase the radio and the SD card adapter kit:
  • http://www.ti.com/tool/wl18xxcom82sdmmc
  • http://www.ti.com/tool/wl1835modcom8b
• Use the TI build-utilities to backport the R8.7 release for the Wilink8 drivers:
  • git clone git://git.ti.com/wilink8-wlan/build-utilites.git
  • use latest release 8.7
• Modify drivers to support Renesas RZA1:
  • In the "wl1271_probe" function of the wlcore/sdio.c file, comment out the "wlcore_probe_of" function call and hard code the IRQ used:

//ret = wlcore_probe_of(&func->dev, &irq, &pdev_data);

//if (ret)

// goto out_free_glue;

/// CUSTOM
irq = 38;

• • In the wlcore/sdio.c file, modify the "wl12xx_sdio_set_power" function to use the gpio the toggle power:

/// CUSTOMIZATION
static int wl12xx_sdio_set_power(struct device *child, bool enable)
{
struct wl12xx_sdio_glue *glue = dev_get_drvdata(child->parent);

printk("WL18XX: wl12xx_sdio_set_power() Called\n");

if (enable) {

printk(KERN_ERR "##########################################\n");
printk(KERN_ERR "WL18XX: wl18xx: Setting Power ON\n");
printk(KERN_ERR "##########################################\n");

gpio_request(98, "sysfs"); // Request the GPIO
gpio_direction_output(98, true); // Set the gpio to be in output mode and on
gpio_export(98, false); // Causes gpio49 to appear in /sys/class/gpio
// the bool argument prevents the direction from being changed

mdelay(70);

printk("WL18XX: wl12xx_sdio_set_power() Power On\n");
return wl12xx_sdio_power_on(glue);
}
else {

printk(KERN_ERR "##########################################\n");
printk(KERN_ERR "WL18XX: wl18xx: Setting Power OFF\n");
printk(KERN_ERR "##########################################\n");

gpio_request(98, "sysfs"); // Request the GPIO
gpio_direction_output(98, false); // Set the gpio to be in output mode and on
gpio_export(98, false); // Causes gpio49 to appear in /sys/class/gpio
// the bool argument prevents the direction from being changed

printk("WL18XX: wl12xx_sdio_set_power() Power Off\n");
return wl12xx_sdio_power_off(glue);
}
}

• • In the wlcore/main.c file, in the "wlcore_irq" function, add the following to the beginning of the function:

   void __iomem *irc1 = IOMEM(0xfcfef804);

   u16 value;

   value = __raw_readw(irc1);

   value = 0x0000;

   __raw_writew(value, irc1);

• Modify the Linux board file "board-rskrza1.c" to make the chosen gpio behave like a proper interrupt:
  • r7s72100_pfc_pin_assign(P4_14, ALT8, DIIO_PBDC_DIS);  /* IRQ6 */

That's it! Hopefully this helps someone.

I added instructions on how to get the Wilink 8 to work here: renesasrulz.com/.../22503.aspx

Good instructions. Thank you for contributing!

For the RSK the default was:

u-boot = single SSPI

dtbs = single QSPI

kernel = dual QSPI

rootfs = dual QSPI

Usually the biggest confusion when moving between single and dual QSPI modes is the SPI addressing. In Dual SPI, each "address" of SPI holds "2 bytes" of data, so for a given 'SPI address range' you would send twice as much 'data'.

> #JLinkExe -speed 15000 -if JTAG $JTAGCONF -device R7S721001_DualSPI -CommanderScript load_spi_kernel_uImage.txt

> JLinkExe -speed 15000 -if JTAG $JTAGCONF -device R7S721001 -CommanderScript load_spi_kernel_uImage.txt

This is only for the kernel. you would also need to program the AXFS rootfs as single as well.

> I changed the boot configuration in u-boot ( xsa_boot  ) to use this "single" parameter.

What do your new u-boot commands look like?

I did flash the AXFS rootfs with the following CommanderScript as well but it did not seem to help:

speed 100000

device R7S721001

rx 100

exec SetCompareMode=0

exec SetVerifyDownload=0

exec SetSkipProgOnCRCMatch=0

loadbin rootfs.axfs.bin,0x18800000

exit

Also, the u-boot command that I am using to boot is:

run xsa1 xsa2 xsa4; set bootargs console=ttySC2,115200 console=tty0 ignore_loglevel root=/dev/null rootflags=physaddr=0x18800000; fdt chosen; bootx 18200000 09800000

Where:

xsa1=sf probe 0; sf read 09800000 C0000 8000
xsa2=fdt addr 09800000 ; fdt memory 0x08000000 0x02000000
xsa3=qspi dual
xsa4=qspi single

The strange thing is that the kernel boots mostly, but hangs half-way. It does not complain about not finding a rootfs.

> I did flash the AXFS rootfs with the following CommanderScript as well but it did not seem to help:

But, when you called the script, did you start JLinkExe with

-device R7S721001

or

-device R7S721001_DualSPI

Since your JLink is connected to Linux, you could also try using "./build.sh jlink" which only uses single QSPI (-device R7S721001) at the moment, so that would be fine for you.

./build.sh jlink output/linux-3.14/arch/arm/boot/xipImage 0x18200000

./build.sh jlink output/axfs/rootfs.axfs.bin 0x18800000

Also, make sure you are using a relativity new version of J-Link. There was an update (at the beginning of the year?) to fix that Jlink would not program correctly past a 16MB address for single SPI (32MB for dual SPI)

> After reflashing it, it successfully boots Linux up until a certain point and then hangs.

That part doesn't make any sense why it would just stop there (unless part of your kernel didn't program correctly).

Maybe after you flash it, you could use md 0x######## in u-boot and just make sure it programmed all the way to the end.

If your kernel started at 0x18200000, and your rootfs started at 0x18800000, that's 6MB of space for your kernel. How big is your kernel? If it is bigger than 6MB, then when you program in your rootfs after the kernel, the rootfs will erase and overright the end of your kernel binary.

I must have some kind of addressing issue. When I reflashed the Kernel, it booted fully. Whenever I seem to flash the rootfs, the subsequent kernel boot hangs. But if I then reflash the kernel, it boots perfectly and mounts the rootfs successfully.

> The pin assignments differ on the RZ/A1L part. Is there a BSP for the RZ/A1L? How can I determine what the GPIO names are for the RZ/A1L? Thank you.

For the most part, the pin assignments are the only thing different between the parts. Before the next BSP release, we'll add in support for RZ/A1L.

But for now, the attached file is what we've been using for RZ/A1L boards. It's a replacement for "arch/arm/mach-shmobile/pfc-rza1.c"

We'll most likely have to add something to menuconfig to select that you have a RZ/A1L instead of RZ/A1H,M before we push it to the github repositories.

NOTE: You have to rename the file from .c.txt back to .c (the forum SW didn't like that it was a .c file)

In the BSP for the RZA1H Dev Kit there is the following array of GPIO names:

static const char * const gpio_names[] = {
"P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5",
"P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", "P1_8",
"P1_9", "P1_10", "P1_11", "P1_12", "P1_13", "P1_14", "P1_15",
"P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", "P2_8",
"P2_9", "P2_10", "P2_11", "P2_12", "P2_13", "P2_14", "P2_15",
"P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", "P3_8",
"P3_9", "P3_10", "P3_11", "P3_12", "P3_13", "P3_14", "P3_15",
"P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", "P4_8",
"P4_9", "P4_10", "P4_11", "P4_12", "P4_13", "P4_14", "P4_15",
"P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", "P5_8",
"P5_9", "P5_10",
"P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", "P6_8",
"P6_9", "P6_10", "P6_11", "P6_12", "P6_13", "P6_14", "P6_15",
"P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", "P7_8",
"P7_9", "P7_10", "P7_11", "P7_12", "P7_13", "P7_14", "P7_15",
"P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", "P8_8",
"P8_9", "P8_10", "P8_11", "P8_12", "P8_13", "P8_14", "P8_15",
"P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
"P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7",
"P10_8", "P10_9", "P10_10", "P10_11", "P10_12", "P10_13", "P10_14",
"P10_15",
"P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7",
"P11_8", "P11_9", "P11_10", "P11_11", "P11_12", "P11_13", "P11_14",
"P11_15",
};

In the rskrza1_bsp/doc/testing directory there is a gpio.txt file that shows how to use these names with SYSFS:

# enable the use of that pin
echo 98 > /sys/class/gpio/export

# set that pin as a GPIO-OUT
echo out > /sys/class/gpio/P7_1/direction

# turn LED0 on, then off
echo 0 > /sys/class/gpio/P7_1/value
sleep 1
echo 1 > /sys/class/gpio/P7_1/value

# if you are done with the pin, you can do this to remove the interface
echo 98 > /sys/class/gpio/unexport

The pin assignments differ on the RZ/A1L part. Is there a BSP for the RZ/A1L? How can I determine what the GPIO names are for the RZ/A1L? Thank you.

> Whenever I seem to flash the rootfs, the subsequent kernel boot hangs.

I think, it is because high byte of address is set up by "Bank Register Write" command, and after the system is reset and starts to read a first command to execute, BAR register still contains 0x01 and the command is actually read from 0x19000000 address, not 0x18000000.

To prevent such behaviour, you need to use some external watchdog chip, and connect the flash's RESET pin together with CPU's RES pin to watchdog's output.

I need to boot the RZ/A1 RSK XIP Kernel out of a single Quad SPI instead of the dual Quad SPI default configuration of the dev kit. We removed the resistor R283 on the chip select line to I2C5 ( which is the secondary Quad SPI ).

In the bsp's u-boot rskrza1.c file, I noticed there is a u-boot option for booting out of a single Quad SPI:

if ( strcmp(argv[1], "single") == 0)
    dual_chip = 0;
else if ( strcmp(argv[1], "dual") == 0)
    dual_chip = 1;
else
    goto usage;

I changed the boot configuration in u-boot ( xsa_boot  ) to use this "single" parameter. When I did that initially, it failed to boot Linux because I forgot to re-flash the kernel into the single SPI device. I reflashed it with the following command:

#JLinkExe -speed 15000 -if JTAG $JTAGCONF -device R7S721001_DualSPI -CommanderScript load_spi_kernel_uImage.txt
JLinkExe -speed 15000 -if JTAG $JTAGCONF -device R7S721001 -CommanderScript load_spi_kernel_uImage.txt

After reflashing it, it successfully boots Linux up until a certain point and then hangs. I made sure to reflash my AXFS filesystem as well, but it did not help. I have not changed any of the JLink commanderscript addresses.

What do I have to do to get Linux to fully boot and mount my filesystem? Thank you.

Here is the hang:

=> run philboot
SF: Detected S25FL512S_256K with page size 512 Bytes, erase size 256 KiB, total 64 MiB
SF: 32768 bytes @ 0xc0000 Read: OK
Current Mode: Read Mode (3-byte Addr) (RZ/A1 reset value)
SF: Detected S25FL512S_256K with page size 512 Bytes, erase size 256 KiB, total 64 MiB
New Mode: Quad I/O Read Mode (4-byte Addr)
Booting Linux...
Booting Linux on physical CPU 0x0
Linux version 3.14.28-ltsi (pclass@Imobius) (gcc version 4.8.3 20140203 (prerelease) (crosstool-NG linaro-1.13.1-4.8-2014.02 - Linaro GCC 2014.02) ) #32 Fri Sep 16 07:36:30 CDT 2016
CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c53c7d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
Machine model: RSKRZA1
debug: ignoring loglevel setting.
Memory policy: Data cache writeback
On node 0 totalpages: 8192
free_area_init_node: node 0, pgdat c003a708, node_mem_map c1fba000
Normal zone: 64 pages used for memmap
Normal zone: 0 pages reserved
Normal zone: 8192 pages, LIFO batch:0
CPU: All CPU(s) started in SVC mode.
pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
pcpu-alloc: [0] 0
Built 1 zonelists in Zone order, mobility grouping off. Total pages: 8128
Kernel command line: console=ttySC2,115200 console=tty0 ignore_loglevel root=/dev/null rootflags=physaddr=0x18800000
PID hash table entries: 128 (order: -3, 512 bytes)
Dentry cache hash table entries: 4096 (order: 2, 16384 bytes)
Inode-cache hash table entries: 2048 (order: 1, 8192 bytes)
Memory: 32008K/32768K available (3124K kernel code, 192K rwdata, 1040K rodata, 143K init, 153K bss, 760K reserved)
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
vmalloc : 0xc2800000 - 0xff000000 ( 968 MB)
lowmem : 0xc0000000 - 0xc2000000 ( 32 MB)
modules : 0xbf000000 - 0xc0000000 ( 16 MB)
.text : 0xbf000000 - 0xbf411414 (4166 kB)
.init : 0xc000a000 - 0xc0013000 ( 36 kB)
.data : 0xc0008000 - 0xc0041018 ( 229 kB)
.bss : 0xc0041018 - 0xc006755c ( 154 kB)
NR_IRQS:16 nr_irqs:16 16
sched_clock: 32 bits at 128 Hz, resolution 7812500ns, wraps every 16777216000000000ns
Console: colour dummy device 80x30
console [tty0] enabled
Calibrating delay loop (skipped) preset value.. 266.09 BogoMIPS (lpj=1041666)
pid_max: default: 32768 minimum: 301
Security Framework initialized
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
CPU: Testing write buffer coherency: ok
Setting up static identity map for 0x72ed628 - 0x72ed680
devtmpfs: initialized
VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
pinctrl core: initialized pinctrl subsystem
NET: Registered protocol family 16
DMA: preallocated 256 KiB pool for atomic coherent allocations
L310 cache controller enabled
l2x0: 8 ways, CACHE_ID 0x410000c8, AUX_CTRL 0x42020000, Cache size: 128 kB
No ATAGs?
hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
hw-breakpoint: maximum watchpoint size is 4 bytes.
bio: create slab <bio-0> at 0
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
Linux video capture interface: v2.00
sh_mtu2 sh-mtu2: ch0: used for clock events
sh_mtu2 sh-mtu2: ch0: used for periodic clock events
NET: Registered protocol family 2
TCP established hash table entries: 1024 (order: 0, 4096 bytes)
TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
TCP: Hash tables configured (established 1024 bind 1024)
TCP: reno registered
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
futex hash table entries: 256 (order: -1, 3072 bytes)
squashfs: version 4.0 (2009/01/31) Phillip Lougher
msgmni has been set to 62
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252)
io scheduler noop registered (default)
io scheduler deadline registered
io scheduler cfq registered
SuperH (H)SCI(F) driver initialized
sh-sci.2: ttySC2 at MMIO 0xe8008000 (irq = 231, base_baud = 0) is a scif
console [ttySC2] enabled
physmap platform flash device: 04000000 at 18000000
Creating 1 MTD partitions on "physmap-flash.0":
0x000000800000-0x000004000000 : "qspi_rootfs"
usbcore: registered new interface driver usb-storage
mousedev: PS/2 mouse device common for all mice
sh-rtc sh-rtc: rtc core: registered sh as rtc0
i2c /dev entries driver
at24 3-0050: 2048 byte at24 EEPROM, writable, 16 bytes/write
i2c-riic i2c-riic.3: version 2013-04-19: 100[kbps]
usbcore: registered new interface driver uvcvideo
USB Video Class driver (1.1.1)
gspca_main: v2.14.0 registered
usbcore: registered new interface driver ov534
usbcore: registered new interface driver ov534_9

You do a watchdog reset. That's what we do in the Linux BSP. It resets everything.