Hi Beammy and Chris,
The level-1 data-cache is setup as write-back by the Linux, not write-through.
Cortex-A9 doesn't support write-through about level-1 data cache,
and if it is setup as write-through, it is treated as uncacheable.
It is a good choice if Beammy used v7_dma_inv_range function. (As Chris had instructed.)
It does "clean (=write-back) and invalidate data cache line" at the both side (cache line) of region,
mcrne p15, 0, r0, c7, c14, 1 @ clean & invalidate D / U line
and does "invalidate data cache line" within the middle of region.
mcr p15, 0, r0, c7, c6, 1 @ invalidate D / U line
Of course, the function should be called before DMA.
Regards,
