RE: enable support to ADV7604 in 3.14 kernel
Hi dylan_mesotic,You should deselect: [*] Autoselect ancillary drivers (tuners, sensors, i2c, frontends)You see: [ ] Autoselect ancillary drivers (tuners, sensors, i2c, frontends)...
View ArticleRE: enable support to ADV7604 in 3.14 kernel
Hi Pecteilis,This is exactly what I want.ADV7604 driver is now enabled in my kernel.Thank you !Regards
View ArticleRE: Confused about CAN receive rules & buffers
FYI, the new CAN driver has been posted:RZ/A1H Group RSCAN Driver Moduleam.renesas.com/.../an_r01an2784eu_rza1h_rscan.jsp
View ArticleConfused about CAN receive rules & buffers
My needs are simple. I want to receive all CAN messages on the bus. Therefore, it seems like I only need one receive rule (with RSCAN0GAFLMj=0 and GAFLDLC=0 so there is no filtering).However, I'm...
View ArticleRE: RZ/A1L RSCAN sample
FYI, the new CAN driver has been posted to the Renesas website:RZ/A1H Group RSCAN Driver...
View ArticleRZ/A1L RSCAN sample
Hi,the only sample for RSCAN I have found so far isan_r01an2511eg0100_rza1h_rsk/Workspace/RSK+RZA1_E2/RZ_A1H_CAN_RSIs there a more sophisticated example available which uses e.g.interrupt handlers?
View ArticleRE: How to invalidate small region of L1 cache after DMA?
In Linux, here is how they invalidate a range of L1 data cache. If you're not using Linux, you can at least use it as sample code.lxr.free-electrons.com/.../cache-v7.S
View ArticleRE: How to invalidate small region of L1 cache after DMA?
Thanks for that. I tried putting the code there into my project. I'm not the best with assembly language, but I think I included it right. However, the assembler didn't like the line:...
View ArticleRE: How to invalidate small region of L1 cache after DMA?
Here's where that 'dcache_line_size' macro is defined:lxr.free-electrons.com/.../proc-macros.SAs for what value it returns (or if it returns the same value every time)....that I don't know
View ArticleRE: How to invalidate small region of L1 cache after DMA?
It worked!! Chris, you just made my day :DDo you happen to know, can I rely on that function to only invalidate the exact bytes of ram that I specify as the start and end? I can't always know whether...
View ArticleRE: How to invalidate small region of L1 cache after DMA?
Cool.I'd guess that the entire cache line gets invalidate as I can't see how the HW logic of the design could do it on a byte by byte basis.I don't know (any maybe that is what you are asking), if...
View ArticleRE: How to invalidate small region of L1 cache after DMA?
Hi Beammy and Chris,The level-1 data-cache is setup as write-back by the Linux, not write-through.Cortex-A9 doesn't support write-through about level-1 data cache, and if it is setup as write-through,...
View ArticleRE: How to invalidate small region of L1 cache after DMA?
Cool. Yes it seems to be working great.I suppose the danger would be if, while the DMA transaction were taking place, some other piece of my code tried to read another piece of memory in the same...
View ArticleRE: How to invalidate small region of L1 cache after DMA?
Hi Beammy,You are right.The dsb instruction ("dsb st" in the v7_dma_inv_range function) completes when:(a) All explicit memory accesses before this instruction complete.(b) All Cache, Branch predictor...
View ArticleHow to invalidate small region of L1 cache after DMA?
I'm doing a DMA transfer from the SPI module to internal RAM. However, if L1 cache is enabled, I can never actually read the data afterwards. I assume I need to invalidate a small region (I'm working...
View ArticleRE: How to invalidate small region of L1 cache after DMA?
By using LDREX STREX CLREX you can savely acces this ram part where a dma engine possible store some datasee this link how to use this assembler instructionsinfocenter.arm.com/.../index.jsp
View ArticleRE: How to invalidate small region of L1 cache after DMA?
Thanks for the extra info. Does anyone know what the actual cache block size for an RZ is? I want to make sure I don't read from the same cache block while DMA is taking place. The manual says 32...
View ArticleRE: How to invalidate small region of L1 cache after DMA?
The line size of L1 data cache is 8 words (= 32 bytes) .You must modify page table by your program to switch caching off outside of a given memory region,and then invalidate TLB entries (and BTB if...
View ArticleRZ/A1H Schematic & Layout
Hi, How to get this information belowr? Thanks1.Rsk + rza1 V2 Starter Kit of schematic( Orcad.dsn file) and Layout files?2.Layout Guide & Design Guide?
View ArticleRE: Rsk + rza1 V2 Evaluation Boards
The RZ/A1H device can read from 2 SPI flash at the same time. This is to increase the speed of reading data. Also, the RZ/A1H can XIP (Execute In Place) from external SPI flash, meaning the CPU can...
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