Hello,
I am replicating the trap&emulate strategy in a Hypervisor using a RZ/T2M development board. The process involves the Hypervisor receiving an exception (load/store access fault) when a VM Guest tries to access a MPU protected address.
1. VM Guest try to access to a MPU protected address;
2. The Hypervisor then reads the value of the HDFAR register, which holds the faulting address causing the Data Abort exception, to proceed with the emulation process.
The attestation of this process was previously verified using the FVP Cortex R52 model, where it displayed the HDFAR value correctly. However, when reading the HDFAR register at RZ/T2M board, the value is not displayed correctly.
Example:
At the following figure HDFAR has the value 0xfffffffe, when the correct value should be 0x9400047c.
Note when we read he HPFAR the value is correct, i.e., 0x94000470. However, since the last byte is reserved, we only have access to value 0x94000470.
Question:
There is any explanation to this HDFAR register behavior?