Hello,
We use a RZ/A2M, osless.
We have a higher prio (prio 5) interrupt, which may take some longer time in some cases.
Therefore we want to re-enable all interrupts ( this can be done by using __enable_irq() ), but also some interrupts with lower priority.
In many CPU's you can update the 'actual mask level' (which is also restored after the actual interrupt).
In that case, when you are in interrupt prio 5, you could update the masklevel to e.g. 7 (lower prio), so a new interrupt with prio 6 can interrupt the 'longer-lasting' interrupt with prio 5, but prio 8 cannot do it.
But in this ARM RZ/A2M we cannot find a solution to update this 'actual mask level'.
When we search on internet, the only way should be to end this interrupt already (by writing to INTC_GICC_EOIR_ADDR), and do a kind of 'simulate' a 'return from interrupt'.
But in that case, the interrupt with prio 8 is also enabled, thus you should have to do extra things like 'disable that interrupt for a while' or maybe by writing prio 7 to INTC.GICC_PMR.LONG temporarily.
The conclusion is thus: such operation looks not beeing so simple in the RZ/A2M.
Or does anyone have a brilliant idea ?