Hi,
According to the user's manual (hardware, rev.2.00) of the RZ / A1H,
3.4 Exception Vector Address at a Reset in Each Boot Mode
In this LSI, the exception vector address at a reset differs depending on the boot mode.
In this LSI, the exception vector at a reset starts from H'0000_0000 (low vector) in boot mode 0
or 1 and from H'FFFF_0000 (high vector) in boot mode 3 to 5.
In this LSI, an on-chip ROM is allocated in area H'FFFF_0000 to H'FFFF_FFFF.
The on-chip ROM has a boot program which executes processing corresponding to the boot mode
set by the MD_BOOT2 to MD_BOOT0 external pins.
If you use boot mode 3, the boot program sets up the SPIBSC (SPI multi I/O bus controller) channel 0
as described in "3.3 Hardware Used in Each Boot Mode", and jumps to H'1800_0000.
So, you can set up clocks, gpio (except pins which SPIBSC channel 0 is using) by your program
starting at H'1800_0000 written in the serial flash memory (connected to SPIBSC channel 0).
Also, you can set up spi module, such as RSPI (Renesas Serial Peripheral Interface) and
SPIBSC channel 1, but you cannot set up SPIBSC channel 0 because your program is running
on the serial flash memory connected to SPIBSC channel 0.
The SPIBSC channel 0 should be set up by a program running on ... e.g. internal RAM.
Regards,