Quantcast
Channel: Forum - Recent Threads
Browsing all 1583 articles
Browse latest View live

RE: Connecting SDRAM memory to the RZ/A1H controller

You would have to connect two 64MByte SDRAM chips to get 128MByte (you can only have up to 64MByte per chip select)You can connect 32-bit SDRAM if you want (16-bit is cheaper, that is why you see more...

View Article


RE: Connecting SDRAM memory to the RZ/A1H controller

I don't need 128MByte SDRAM, only 128MBit.

View Article


Connecting SDRAM memory to the RZ/A1H controller

Hello! I've never worked with Renesas controllers. Is it possible to connect 128MBit 32bit SDRAM to RZ/A1H controller ? I saw the only 16bit SDRAM in connection examples. And i'd like to execute code...

View Article

RE: QSPI flash in DDR mode

Yes, but each manufacture does id a little different, so you have to pay close attention.Also, you have to pay attention to the setup and hold times of the DDR mode. Sometimes the clock rate might be...

View Article

RE: QSPI flash in DDR mode

I can't find any mention about DDR mode in the User's manual.

View Article


QSPI flash in DDR mode

 Does RZ/A1H controllers support QSPI flash in DDR mode?

View Article

RE: Problem booting linux-3.14 on custom board

I assume you are using SCIF2 on the same pins that the RSK used (because you already configured u-boot correctly)Even though the kernel check for the DTB early in boot, I have had the same looking log...

View Article

Problem booting linux-3.14 on custom board

Hello,I have a custom board based on RZA1H, I use U-boot 2015.01 and linux-3.14 from Renesas Github repositories.The board is really similar to the RSKRZA1 but had a 12Mhz Crystal instead of 13.33Mhz....

View Article


RE: How to add RGA library to existing e2studio project?

What is the folders that you can not find?If this is the common folder, try to copy from <an_r01an2162ej0200_rza1h_other\workspace\RZ_A1H_RGA_Sample\RGA_Sample\armcc\common> folder.I could find...

View Article


DMA Link mode problem

Hi,I try to get DMA in link mode working, but when DMA is enabled, the DER bit of the Channel Status Register is set. According to the user manual, this bit is set when the LV (Link valid) bit of the...

View Article

RE: SDRAM

Since you will have non-continuous memory (32MB at address 0x08000000, 32MB of nothing at 0x0A000000, and then 32MB at address 0x0C000000), you will have to:1. edit the device tree and put in each...

View Article

SDRAM

Hi all,We have RZA1H CPU based Hardware with two chips of SDRAM of each 32MB in size and SDRAM chips are interfaced to CS2 and CS3 space.And we are loading RZRSK BSP1.2 version and the hardware is...

View Article

RE: Booting from serial flash

If you are using an RZ/A device, it does not have internal ROM. But, when booting from external serial flash, it will execute the code directly in the serial flash, so you just need to download your...

View Article


Booting from serial flash

Hello! I don't understand, how to boot from serial flash memory? Must i write my own bootloader and flash it in internal ROM or what ? Must i use CFI compliant flash?

View Article

RE: Problem booting linux-3.14 on custom board

Hello,Thanks for your reply Chris.You were right, it was related to the devicetree. Do you have any ideas why the kernel is stuck like this because of the devicetree ? I mean there is no relevant...

View Article


RE: Problem booting linux-3.14 on custom board

Honestly, the first time I ran into this, I spent hours tracking it down going line by line during the kernel init code (because I thought it was XIP Linux related) until I finally figured it out, and...

View Article

RE: Booting from serial flash

So i even mustn't set up clocks, gpio, spi module ?

View Article


RE: DMA Link mode problem

HiIf you enabled L1 data cache and/or L2 cache, write-back them and drain write-buffer before starting DMA.I think that you should allocate coherent region for link descriptors.Regards,

View Article

RE: Booting from serial flash

Hi,According to the user's manual (hardware, rev.2.00) of the RZ / A1H,3.4 Exception Vector Address at a Reset in Each Boot ModeIn this LSI, the exception vector address at a reset differs depending on...

View Article

RE: SDRAM memory maximum frequency

Hi,According to the user's manual (hardware, rev.2.00) of the RZ/A1H,In the "Figure 6.1 Block Diagram", the maximum frequency for external bus clock (CKIO) is 66.67MHz. Regards,

View Article
Browsing all 1583 articles
Browse latest View live