RZ/A1L SCI with FIFO Transmit interrupt

I am using SCI interface with FIFO for RZ/A1L micro processor.

Could anyone provide sample code for initialisation, and interrupt handling code.

Actually, I am not understanding the interrupt clearing part for TXI interrupt.

When I initialise the SCI interface and enable TIE bit in SCSCR register, the interrupt routine keep on executing and blocking the CPU operation.