RZ/A1L TXI interrupt handling for SCI with FIFO

Could anybody provide a sample code for handling TXI interrupt?

I am able to set the registers properly and Receive and transmit data correctly. but not sure how to handle the TXI interrupt.

At the time of initialization, I am enabling TIE and RIE bit in SCSCR register but as the register gets initialized, I am continuously receiving TXI interrupt.

Is it like, when we transmit any data then only need to enable TIE bit? Please suggest the way to handle in the code.